Freescale Semiconductor /MKE14D7 /PORTE /PCR3

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Interpret as PCR3

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (RESERVED)RESERVED 0 (0)PE 0 (RESERVED)RESERVED 0 (RESERVED)RESERVED 0 (RESERVED)RESERVED 0 (RESERVED)RESERVED 0 (RESERVED)RESERVED 0 (RESERVED)RESERVED 0 (000)MUX0 (RESERVED)RESERVED 0 (0)LK 0 (0000)IRQC0 (RESERVED)RESERVED 0 (0)ISF 0 (RESERVED)RESERVED

IRQC=0000, LK=0, ISF=0, MUX=000, PE=0

Description

Pin Control Register n

Fields

RESERVED

no description available

PE

Pull Enable

0 (0): Internal pullup resistor is not enabled on the corresponding pin.

1 (1): Internal pullup resistor is enabled on the corresponding pin, if the pin is configured as a digital input.

RESERVED

no description available

RESERVED

no description available

RESERVED

no description available

RESERVED

no description available

RESERVED

no description available

RESERVED

no description available

MUX

Pin Mux Control

0 (000): Pin disabled (analog).

1 (001): Alternative 1 (GPIO).

2 (010): Alternative 2 (chip-specific).

3 (011): Alternative 3 (chip-specific).

4 (100): Alternative 4 (chip-specific).

5 (101): Alternative 5 (chip-specific).

6 (110): Alternative 6 (chip-specific).

7 (111): Alternative 7 (chip-specific).

RESERVED

no description available

LK

Lock Register

0 (0): Pin Control Register fields [15:0] are not locked.

1 (1): Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.

IRQC

Interrupt Configuration

0 (0000): Interrupt/DMA request disabled.

1 (0001): DMA request on rising edge.

2 (0010): DMA request on falling edge.

3 (0011): DMA request on either edge.

4 (0100): Reserved.

8 (1000): Interrupt when logic zero.

9 (1001): Interrupt on rising edge.

10 (1010): Interrupt on falling edge.

11 (1011): Interrupt on either edge.

12 (1100): Interrupt when logic one.

RESERVED

no description available

ISF

Interrupt Status Flag

0 (0): Configured interrupt is not detected.

1 (1): Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

RESERVED

no description available

Links

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